AV143 – Virtex® Ultrascale+™

Schémas

Specs techniques

12-bit 3.2/6.4 Gsps ADC
The AV143 Analog to Digital conversion is performed by one Texas Instruments ADC12DL3200 12-bit 3.2/6.4 Gsps ADC
The AV143 provides two front panel SMPM connectors for analog input.
Single ended input signals are AC coupled with an input bandwidth from 10 MHz to more than 8 GHz with TBD dBm input level.

12-bit 3.2/6.4 Gsps DAC
The AV143 Digital to Analog conversion is performed by one Texas Instruments DAC12DL3200 12-bit 3.2/6.4 Gsps DAC.
The AV143 provides two front panel SMPM connectors for analog output.
Single ended output signals are AC coupled with an output bandwidth from 10 MHz to more than 8 GHz with TBD dBm output level (NRZ).

Clock
The AV143 provides one ultra-low jitter clock synthesizer locked on a 100 MHz internal reference. The AV143 supports a 10 to 500 MHz external reference input from a front panel SMPM connector. A reference output is available on a front panel SMPM connector.
An external clock input for the ADC and DAC is supported from one front panel SMPM connector.
External clock frequencies from 1.6 GHz to 6.4 GHz are supported.

Trigger and Synchronization
The AV143 provides one front panel SMPM connector for external trigger input.

FPGA
The AV143 is fitted with a Xilinx^® Virtex^® Ultrascale+™ VU7P, VU9P or VU13P user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR4 SDRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex Ultrascale+ VU13P FPGA includes 3,780 K logics cells, 94.5 Mbit of RAM blocs, 360 Mbit of Ultra RAM, 4 PCIe GEN3x16 interface blocs and 12,288 DSP48 slices for an impressive processing power of more than 19 TMACs.
The FPGA is delivered in -2 speed grade.

Memories
The AV143 includes two 1G64 DDR4-2666 SDRAM memory banks and one 2 Gbit QSPI FLASH used to store multiple FPGA configuration files.

VPX interface
The AV143 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra-Thin Pipes for Control Plane and two User Defined Ultra-Thin Pipes on P1. The AV143 also supports 22 LVDS differential pairs configurable as 44 single-ended LVCMOS on P2 plus USB2.0 and UART for supervision and monitoring.
The AV143 features one low phase noise clock generator able to synthesize clock references for the FPGA GTYs from 60 MHz to 820 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1, 2 and 3 and XAUI 10Gbit Ethernet up to 28 Gbps.

Microcontroller
The AV143 features a 32-bit 200 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports a USB 2.0 and a UART interfaces accessible on the VPX P2 user IO pins through an ApisSys AR113 Rear Transition Module.
The microcontroller firmware includes all necessary features for board monitoring and supervision.

Firmware
The AV143 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV143 hardware resources.
A base design is provided which demonstrates the use of the AV143 and gives users a starting point for firmware development. The AV143 firmware package is supported on the Xilinx VIVADO^® 2022.1 design suite.

Software
The AV143 is delivered with software drivers for Windows 10 and Linux.

Ruggedization
The AV143 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 ruggedization levels supported are EAC4, EAC6, ECC3 and ECC4.

Livrables

Ruggedization

ECCN

ECCN number: 3A002h1

Applications

• Electronic Warfare – Electronic Attack
• DRFM
• Radar Transmitter / Receiver
• Wideband Communication